Saber仿真开关电源设计

® Power Converter Design Using the Saber Simulator A Step-By-Step Guide to the Design of a Two-Switch, Voltage-Mode, Forward Converter Using the Saber Simulator By Steve Chwirka Analogy, Inc. Beaverton, Oregon (503) 626-9700 Page 1 of 32 Page 2 of 32 ® Table of Content 1.0 Scope of Document 3 2.0 Specifications 3 2.1 Input Specifications 3 2.2 Output Specifications 3 2.3 Other Specifications 3 3.0 Step-By-Step Design Process 4 3.1 Open Loop Design 4 3.1.1 Define the Duty Cycle and Turns Ratio of the Transformer 4 3.1.2 Design the Rectifier and Filter Capacitor (Optional Section) 5 Validate the Rectifier and Filter Capacitor using Saber 9 3.1.3 Output Filter Design 10 Inductor Design 10 Capacitor Design 11 3.1.4 Validate the Open Loop Design using Saber 11 3.2 Compensator Design using an Averaged Model 15 3.2.1 Validate the Averaged Model using Saber 16 3.2.2 Open-Loop AC Analysis 18 3.2.3 Designing the Compensation Circuit 18 3.2.4 Validate the Compensator Design using Saber 21 3.2.5 Validate the Closed Loop Parameters using Saber 21 3.3 Modulator Design and Final Closed Loop Simulation 23 3.3.1 Validate the Modulator Design using Saber 25 3.3.2 Validate the Closed Loop Design using Saber 27 3.4 Final Component Level Design 29 ® 1.0 Scope of Document This engineering document will guide the reader through the step-by-step design of a two switch, voltage mode, forward power converter using the Saber Simulator. In the process, we will describe typical design considerations and problems and how to overcome them. Validation of each step in the design process will be performed using Saber. 2.0 Specifications The following specifications will be used to design the power converter. 2.1 Input Specifications Line Input 150Vdc, ± 6V Pin(max) = = 30/.85 35 Watts 2.2 Output Specifications Vout 15Vdc Vout(ripple) ≤ 25mV p-p Iout 50mA to 2A Iout(ripple) ≤100mA p-p Pout(max) = (15V)(2A) 30 Watts 2.3 Other Specifications Efficiency ≥ 85% Switching Frequency 200KHz (derived) Pout(max) Eff Page 3 of 32 ® 3.0 Step-By-Step Design Process This section details the steps necessary to design the power converter. 3.1 Open Loop Design 3.1.1 Define the Duty Cycle and Turns Ratio of the Transformer The basic relationship in a forward converter is Vout ≅ (Vin)(1 / n)(D) where Vout =dc output voltage n = turns ratio = np / ns D = duty cycle Given that Vout = 15VDC and Vin = 150 VDC, we see that (1 / n)(D) must equal 0.1 i.e. 15 = (150)(.1) The duty cycle of a forward converter should not exceed .5. Therefore we will choose a value which is between 0 and 0.5. In this example we choose D = 0.3, approximately the midpoint of the range. Therefore we know (1 / n)(D) = .1 or 1 / n = .1 / D = .1 / .3 = 1/3 so n = 3 The next step is to define the maximum and nominal duty cycle which include the output diode losses. These values will be needed for future calculations. n = turns ration = np / ns = 3 Vin(min) = 144 (per specifications) Vout = 15V + (output diode losses ≅ .85V) = 15.85V ∴ Dmax = 15.85 / (144)(1/3) = .3302 Note that this is less than .5, the maximum duty cycle allowed in a forward converter. Dmax = Vout(Vin(min))(1/n) Page 4 of 32 ® Vin(nom) = 150Vdc ∴ Dnom = 15.85 / (150)(1/3) = .317 Note that this is greater than .3 calculated earlier because it takes the output diode into account. 3.1.2 Design the Rectifier and Filter Capacitor (Optional Section) Note: A full-wave bridge rectifier will be used to allow the design of a smaller filter capacitor. FIGURE 1 shows the rectified waveform, the desired DC input voltage of 150VDC and the result- ing input ripple voltage (Vr) . From FIGURE 1: Vpeak = Vin(ac) / .707 = 115 / .707 = 162.7 162.7 - (rectifier diode drops) ≅ 161.3V (where Vd ≅ .7) Vdc = 150 V Vmin = Vdc - (Vpeak - Vdc) = 150 - (161.3 - 150) = 138.7V Dnom = Vout Vin(nom))(1/n) Vr 11.3 11.3 Vpeak Vdc Vmin t1 t2 T3 Rectified input voltage with filter capacitor Rectified input voltage without filter capacitor θ FIGURE 1 Filtering of Rectified Input Voltage Page 5 of 32 ® The input filter capacitor value can be found in two ways Input Capacitor Value - Method 1 C = (Idc)(T3) / Vr Idc = Pin(max) / Vdc = 35W / 150V = .233A Vr = (2)(Vpeak-Vdc) = (2)(11.3) = 22.6V T3 = Time the capacitor must deliver its energy to the circuit Solving for T3: T3 = t1 + t2 t1 = (1/4)(1/f) where f = input frequency = 60Hz = (1/4)(1/60) = 4.166 msec Note: Most text books at this point assume that the input ripple is small and therefore that t2 ≅ t1 which would yield T3 = 4.166 msec + 4.166 msec = 8.33 msec However, this is not the case in many designs. Therefore we need to use the following equations to calculate t2: Referring to FIGURE 1: Vmin = Vpeak(Sinθ) θ = θ = Sin-1(138.7 / 161.3) = 59.3o We know that where f = input freq = 60Hz ∴ = (59.3)(1/2)(1/60) / 180o t2 = 2.745 msec Sin-1 Vmin Vpeak 180o (1/2) (1/f) = θ t2 t2 = (θ)(1/2)(1/f) 180o Page 6 of 32 ® In other words: From input filter capacitor design equations we had C = (Idc)(T3)/ Vr Vr = 22.6V Idc = .233A T3 = t1 + t2 t1 = 4.166 msec t2 = 2.745 msec ∴ T3 = 4.166 msec + 2.745 msec = 6.911 msec Note the significant difference between 6.911 msec and the approximate calcula- tion of 8.33 msec. Final Calculation: C = (.233A)(6.9116 msec) / 22.6 V = 71.36 uF Input Capacitor Value - Method 2 Using E = CV2 / 2 = 71.36 uF t2 = Sin-1 Vmin Vpeak 1 2 1 f 180o C = (Pin(max))(T3) (1/2)(Vpeak2 - Vmin2) = (35)(6.9116m) (1/2)(161.32 - 138.72) Page 7 of 32 ® Once the filter capacitor has been calculated, validate using the schematic shown in Figure 2. This shows l an input source: v.* m p = tran=(sin=(va=162.7, f=60)) note: 115VAC / .707 = 162.7Vpeak l filter capacitor with value of 71.36 uF as calculated l load resistor which forces Pin(max) = 35W P = V2 / R ⇒ R = V2 / P = (150)2 / 35 = 642.8Ω FIGURE 2 Circuit Used to Verify the Rectification and Filter Capacitance for a 35 Watt 115 Vac Input Page 8 of 32 ® 3.1.2.1 Validate the Rectifier and Filter Capacitor using Saber View the results shown in Figure 3 and compare with the calculated values. Note: Vpeak ≅ 161.3 Vmin ≅ 138.7 Voltage across the input filter capacitor (V): t(s) (1)p 76m 78m 80m 82m 84m 86m 88m 90m 92m 94m 96mt(s)138 140 142 144 146 148 150 152 154 156 158 160 162 (V) FIGURE 3 Voltage Across the Input Filter Capacitor Page 9 of 32 ® 3.1.3 Output Filter Design This section will describe the design of the output filter which consist of a 2-pole LC design. The output inductor will be calculated to limit the peak-to-peak ripple current, and the output capacitor will be calculated to limit the peak-to-peak output ripple voltage. 3.1.3.1 Inductor Design The current waveform through the filter inductor is shown in Figure 4. The allowed peak-to-peak current in the inductor is determined by the minimum load current specification. From the spec. we have Iout(min) = .05A. If the load current goes below .05A, the converter will go into discontinuous mode (the inductor current goes to zero). See Figure 5. Io = 2 A (max) Iripple toff toff(max) = 1 - D(min) fswitching where fswitching = 200 KHz FIGURE 4 Current through the Filter Inductor Io(min) = .05A Max Ripple CurrentMax Ripple Current Allowed = (2)(Io(min)) = (2)(50mA) = 100mA p-p di dt (A) (t) FIGURE 5 Current Through Filter Inductor .05A 0 .1A Page 10 of 32 ® From Figure 4, it can be seen that the inductor’s current decreases during the OFF time of the switch. In order to prevent discontinuous operation, the inductor current must not go to zero dur- ing this OFF time (at minimum load of .05A per the spec.) Therefore the inductor will be sized to limit the peak-to-peak current to .1A p-p. We know VL = L (di/dt) L = VL / (di/dt) where VL = 15V dt = max off time (see Figure 4) =(1 - Dmin) / (f switching ) = (1-0.3030) / 200KHz ≅ 3.5 us di = .1A ∴ L = 15 / (.1 / 3.5u) ≅ .53 mH 3.1.3.2 Capacitor Design The Vout(ripple) specification, along with the calculated ripple current coming through the induc- tor, determine the size of the output capacitor. The following is used to calculate the capacitor value: Iripple = .1A f = 200KHz Vripple = .025V (from spec) ∴ C = (1/8) (.1) / (200K)(.025) = 2.5 uF Note that the ESR of the capacitor must not exceed: ESRmax = ∆V / ∆I = .025 / .1 = 0.25Ω or the ripple voltage will increase. 3.1.4 Validate the Open Loop Design using Saber Figure 6 shows the Open Loop configuration C = Iripple (1/8)(f)(Vripple) Page 11 of 32 ® This is the Open Loop configuration of the Forward (two switch) converter. It is used to design the transformer’s turns ratio and Inductance, the output filter, the Duty Cycle and switching fre- quency. The Open Loop design can then be simulated and validated to make sure the output volt- age is correct based on a certain Duty Cycle, the output ripple voltage & ripple current are correct, etc. Note: nominal values for input voltage = 150Vdc max output current for load = 2A (Rload = 7.5Ω) duty cycle = nominal = .317 switching frequency = 200kHz values for L, C, ESR Run transient analysis Check: with Vin = 150V, D = .317, n = 3, Vout should be 15V IL ripple should be .1A p-p Vout ripple should be approx. .025V p-p FIGURE 6 Open Loop Configuration of the Forward Converter Page 12 of 32 ® Figure 7 shows the results of the Open Loop simulation. Note that this validates the transformer’s turns ratio, the output filter design, duty cycle, and switching frequency. Figure 8 shows an expanded view of the inductor current and validates the ripple current (100mA p-p). Figure 9 shows an expanded view of the output voltage and validates the ripple voltage (25mV p-p) FIGURE 7 Open Loop Simulation Results Simulation Results for the Forward, Voltage Mode, Open Loop circuit (A): t(s) (1)i(l.l1) (V): t(s) (1)vout 0 50u 100u 150u 200u 250u 300u 350u 400u 450u 500ut(s) -200m 0 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 (A) -4 -2 0 2 4 6 8 10 12 14 16 18 20 (V) Inductor current Output Voltage Page 13 of 32 ® FIGURE 8 Inductor Ripple Current Simulation Results for the Forward, Voltage Mode, Open Loop circuit (A): t(s) (1)i(l.l1) (V): t(s) (1)vout 370u 380u 390u 400u 410u 420u 430u 440u 450u 460u 470ut(s) 1.825 1.85 1.875 1.9 1.925 1.95 1.975 2 2.025 2.05 2.075 2.1 2.125 2.15 (A) 16.25 16.5 16.75 17 17.25 17.5 17.75 18 18.25 18.5 18.75 19 19.25 19.5 (V) Simulation Results for the Forward, Voltage Mode, Open Loop circuit (A): t(s) (1)i(l.l1) (V): t(s) (1)vout 370u 380u 390u 400u 410u 420u 430u 440u 450u 460u 470u 480u 490u 500ut(s)1.675 1.68 1.685 1.69 1.695 1.7 1.705 1.71 1.715 1.72 (A) 14.75 14.8 14.85 14.9 14.95 15 15.05 15.1 15.15 15.2 (V) FIGURE 9 Output Ripple voltage Page 14 of 32 ® 3.2 Compensator Design using an Averaged Model The averaged circuit shown in Figure 10 lets you analyze the power supply without its switching circuitry. Using this averaged circuit, you can perform three types of simulations: an open-loop transient analysis, an open-loop small-signal AC analysis, and a closed-loop analysis. These sim- ulations will provide the needed information to design and validate the compensation circuit. This configuration is use to perform several simulations/analyses. The designer can first perform an open loop transient simulation to validate that the average model is providing the correct out- put voltage for a given control voltage. This transient simulation is also used to set up the operat- ing point for the small signal AC simulation. The next simulation performed is a small signal ac to evaluate the “Control to Output” transfer function. The results are used to design the compensa- tor circuit. Once the compensator circuit is designed, it can be included in another small signal ac simulation to validate the compensator and the feedback has the correct frequency response. The final simulation which can be done from this schematic is a closed loop transient analysis. This will validate that the closed loop circuit (using the averaged model) yields the correct control voltage and Duty cycle as expected by the designer. FIGURE 10 Averaged Configuration of the Forward Converter Page 15 of 32 ® To determine the control voltage for the input to the averaged model, the following control-to-out- put relationship for the forward converter is used: where Vout = 15V Vin = 150V n = 3 Vramp = 2.5V Vd = 0.85V Rearrange the equation to determine the control voltage: 3.2.1 Validate the Averaged Model using Saber Using the Saber simulator and the averaged circuit shown in Figure 10, an open-loop transient analysis is performed to verify the averaged model, and to set up the operating point for the small signal ac simulation. The results are plotted along with the results from the open loop circuit sim- ulation and are both shown in Figure 11. Note the averaged model results track the switching cir- cuit results very well. V out Vin 1 n ---- V c V ramp -----------------------××       Vd–= V c V ramp n V out Vd+ Vin -------------------------------×× 0.7925= = FIGURE 11 Averaged Model vs. Switching Circuit Simulation Results for the Forward, Voltage Mode, Averaged circuit (A) : t(s) (6)i(l.l1) (8)i(l.l1) (V) : t(s) (6)vout (8)vout 0 50u 100u 150u 200u 250u 300u 350u 400u 450u 500u t(s) -200m 0 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 (A) -4 -2 0 2 4 6 8 10 12 14 16 18 20 (V) Inductor Current Output Voltage Page 16 of 32 ® Figure 12 shows the expanded view for the inductor current. Figure 13 shows the expanded view for the output voltage. FIGURE 12 Inductor Current (Switching vs. Averaged) Simulation Results for the Forward, Voltage Mode, Averaged circuit (A): t(s) (6)i(l.l1) (8)i(l.l1) (V): t(s) (6)vout (8)vout 160u 180u 200u 220u 240u 260u 280u 300u 320u 340u 360u 380u 400ut(s) 1.825 1.85 1.875 1.9 1.925 1.95 1.975 2 2.025 2.05 2.075 2.1 2.125 (A) 16.25 16.5 16.75 17 17.25 17.5 17.75 18 18.25 18.5 18.75 19 19.25 (V) FIGURE 13 Output Voltage (Switching vs. Averaged) Simulation Results for the Forward, Voltage Mode, Averaged circuit (A): t(s) (6)i(l.l1) (8)i(l.l1) (V): t(s) (6)vout (8)vout 150u 175u 200u 225u 250u 275u 300u 325u 350u 375u 400u 425u 450u 475u 500ut(s) 1.65 1.655 1.66 1.665 1.67 1.675 1.68 1.685 1.69 1.695 1.7 1.705 (A) 14.6 14.65 14.7 14.75 14.8 14.85 14.9 14.95 15 15.05 15.1 15.15 (V) Page 17 of 32 ® 3.2.2 Open-Loop AC Analysis The next simulation performed using the averaged circuit is an open loop small signal ac analysis. The results are used to evaluate the control-to-output transfer function. This information is then used to design the compensator circuit. Figure 14 shows the frequency response of the control-to- output transfer function. It can be seen that the output filter yields a two pole roll off and a phase of close to 180 degrees: 3.2.3 Designing the Compensation Circuit The compensator design will yield a 0dB crossover at approximately one quarter the switching frequency, and compensate the two-pole roll-off (180° phase) to approximate a single-pole roll- off (90° phase). The compensator will need two zeros to cancel out the effects of the two poles of the output filter. The frequency of the two zeros will be one-half the resonant frequency of the fil- ter. The compensator will add in another pole at one-quarter the switching frequency, which can- cels the effects of the ESR of the capacitor (zero). The approximate net results yield a single-pole roll-off at the crossover frequency. Phase/Gain plot of the "Control voltage to Output" transfer function DB(V): f(Hz) (4)vout DEG(V): f(Hz) (4)vout 100m 1 10 100 1k 10k 100k 1meg 10meg 100megf(Hz) -140 -120 -100 -80 -60 -40 -20 0 20 40 60 DB(V) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 DEG(V) FIGURE 14 Phase/Gain plot of the Control-to-Output transfer function Phase Gain Page 18 of 32 ® Figure 15 shows the compensator circuit chosen . Find the desired break points for the above compensator fz1 and fz2 = (1/2)(resonant freq of output filter) ∴ fz1 = fz2 = (1/2)(4.3KHz) = 2.15 KHz fp2 = (1/4)(switching freq) = (1/4)(200KHz) = 50 KHz Calculate the values for R2 and R3 such that the high frequency gain at the desired crossover (50 KHz) yields an overall gain of 0 dB. From the Bode plot of the open-loop circuit, it can be seen that to have a crossover (0 dB) at 50 KHz, there needs to be an additional 16.37 dB of gain. An additional 3 dB of gain is required since there will be a pole effect at 50 KHz (due to the pole of the integrator which is added via the compensator fp2). ∴ R2 / R3 = (16.37 + 3) dB = 19.37 dB where 19.37 dB = log-1(19.37 / 20) = 9.3 Choose R2 = 50K. We now have 50K / R3 = 9.3 R3 = 50K / 9.3 = 5.38K The gain required at fz1 and fz2 is Av(2.15KHz) = Av(50KHz)(2.15K / 50K) = 9.3 (2.15K / 50K) = .4 FIGURE 15 Type 10 Compensation Network where fR = .159 LC√ = .159 √(.53m)(2.5u) ≅ 4.3 KHz Page 19 of 32 ® The gain at 2.15 KHz is determined by R2 / (R3 + R1) ∴ R2 / (R3 + R1) = .4 R1 = (R2 / .4) - R3 R2 = 50K R3 = 5.28K ∴ R1 = (50K / .4) - 5.38K = 119.62K The capacitors are calculated as follows Calculate the value of R4, which provides a voltage divider for the 15V output. The reference voltage used is 5V, which means the value of R4 must be specified so that the 15V output is divided down to 5V: Solving for R4 yields: R4 = 62.5k. Therefore, final values for the compensator are: R1 119.62k R2 50k R3 5.38k R4 62.5k C1 618 pF C2 1479 pF fz1 = fz2 = 1 2ΠR1C1 1 2ΠR2C2 = = 2.15 KHz ∴ C1 .159(R1)(fz1) = C2 .159(R2)(fz2) = = = .159 .159 (119.62K)(2.15K) (50K)(2.15K) = = 618 pF 1479 pF 15 R4 R4 R3 R1+( )+---------------------------------------------     5= Page 20 of 32 ® 3.2.4 Validate the Compensator Design using Saber With the compensator design complete, another small signal ac simulation is performed to vali- date circuit response. Figure 16 shows the results. Note the 0dB crossover is now at 50kHz and the phase margin is approximately 50° 3.2.5 Validate the Closed Loop Parameters using Saber Continuing to use the averaged circuit shown in Figure 10, the first closed-loop simulation is per- formed with the averaged model. This simulation validates the previous calculated parameters by having the system solve for them. Verify the following: (See Figures 17 & 18) Vout (should be 15 volts) Vc (Control Voltage) (should be approximately .7925) Duty Cycle (should be approximately .317) Phase/Gain plot which includes the effects of the compensator design (Note: phase margin is 50 deg) DEG(V): f(Hz) (4)vc_c DB(V): f(Hz) (4)vc_c 100m 1 10 100 1k 10k 100k 1meg 10meg 100megf(Hz) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 DEG(V) -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 DB(V) M1 Y1: -161.5288m X1: 50.0225k M1 FIGURE 16 Phase/Gain plot (Post Compensator Design) Phase Gain Page 21 of 32 ® FIGURE 17 Output Voltage Closed loop simulation using the average model (Note: vout = 15 volts ) (V): t(s) (5)vout 0 50u 100u 150u 200u 250u 300u 350u 400u 450u 500u t(s) 14.999 14.9992 14.9994 14.9996 14.9998 15 15.0002 15.0004 15.0006 15.0008 15.001 (V) FIGURE 18 Duty Cycle and Control Voltage as solved by the system Closed loop simulation using the average model (Note: duty cycle=.317, & control voltage Vc=.7927) (-) : t(s) (5)....@"pwmsw_fd#175") (V): t(s) (5)vc_c 130u 140u 150u 160u 170u 180u 190u 200u 210u t(s) 317.06m 317.07m 317.08m 317.09m 317.1m 317.11m 317.12m 317.13m 317.14m 317.15m 317.16m (-) 792.66m 792