IBM

D. P. Seraphim I. Fei n berg Electronic Packaging Evolution in IBM A quarter century of innovation in the development of packaging for semiconductors has culminated in the announce- ment of the IBM 4300 Series of computers and the IBM 3081. This technology has been built on a broad and expanding base starting with packaging for the 1400 Series in the late 1950s. In the next series, Systeml360, IBM chose to follow a unique approach which employed solder joints for the semiconductor connections, allowing ultimately a higher density and total number of interconnections compared to the rest of the industry. This has driven the packaging at the module level to achieve extremely high density and has led to multichip interconnections and multilayers on this jirst level of package. The dramatically increasing circuit function at the module level requires area arrays of pins to be able to get enough of them in a small area. Thus the next level (second level) of packaging has likewise been driven to provide many layers of dense interconnections to link to the module pins. New types of plated through holes join the many layers of interconnection. The highlights of the technical approaches which have been developed over the twenty-jive-yearperiod are discussed briefly in this paper. Introduction The increasing complexity of electronic packaging in IBM in this last quarter century has been driven by increasing integration on the semiconductor chip and the growth of computing power and performance in systems. Projection of wiring and wiring density for circuits has been treated at various levels of sophistication [l-31 for chips and for packages. The initial empirical approach began in the early 1960s based on the systems that had been built by then. It was shown by Rent [l] that the number of terminals T supplying the input and output to a set of circuit functions was exponentially dependent on the total number of circuits C, T = ACP, where A and p are constants. In the original evaluation by Rent, A was 4 while p was near 213. By using this relationship, it is possible to break up the entire packag- ing interconnection system into clusters of circuits and into sets of connected interfaces, some of which are pluggable. These are the chips, the modules which may contain one or more chips, the cards, and the back panels (or boards), each of which contains a function or func- tions. The Rent-like trend line is illustrated in Fig. 1 for inputloutput terminals versus maximum circuits per com- ponent. The length of wire interconnection within these packag- ing levels increases as the product of the number of terminals of the subsets within the function, the number of interconnections per terminal, and the average length. For example, the interconnection length required on a module is proportional to the product of the number of chips and the number of terminals per chip. One intercon- nection obviously has two terminals but quite often a terminal can be common to several interconnections. Likewise, several inputs can be connected in common to a transistor. Using these considerations, a statistical interconnection length has been devised which includes the global wiring. The increasing size of the system causes the global wiring to increase. These global wires are the controls for the functions, data flow for the system, instruction data path, and memory data path. Copyright 1981 by International Business Machines Corporation. Copying is permitted without payment of royalty provided that ( I ) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract may be used without further permission in computer-based and other information-service systems. Permission to republish other excerpts should be obtained from the Editor. 617 D. P. SERAPHIM AND I. FEINBERG IBM J. RES. DEVELOP. VOL. 25 NO. 5 SEPTEMBER 1 9 8 1 I I Maximum circuits per package component Figure 1 Trend of inputloutput terminals versus circuits on modules. Figure 2 The 1401 System SMS electronic package. Printed circuit cards which are field-replaceable units are plugged into a back panel. The back panel is wire wrap technology. The thrust for high performance drives the package designer to eliminate factors which delay time of signal propagation or cause excessive capacitive or inductive loading on the circuits. The performance is increased by decreasing the spacing between the components. Indeed, what used to be accomplished on the second level of packaging and in cabling is now better accomplished on the chip or module while the package itself with its dense multilayer interconnection largely replaces the cabling. 618 D. P. SERAPHIM AND I. FEINBERG Figure 3 The Systed360 Model 30 SLT electronic package. Printed circuit cards plug into a printed circuit back panel. One card can be seen to contain as many as 12 SLT modules. Over the past few decades the dominant packaging materials have been ceramic with screened noble fritted metal interconnections for the first-level packages (chip carriers) and epoxy-glass composite dielectric with cop- per interconnections for the second-level packages (the printed circuit cards and boards). Signal and power grids and interconnections have been greatly increased through the migration of printed circuits from structures which provided one signal plane prior to 1960, two signal planes with one or two embedded power planes in the early l%Os, to today’s packaging environ- ment [4-91 where 10 to 20 multilayer designs are common- place. Accompanying this evolution was the ability to manufacture carriers with increasingly smaller line widths, closer spacings, smaller hole sizes, and greater aspect ratios (aspect ratio equals thickness divided by hole diameter). This has resulted in the use of fewer components and has reduced total packaging costs per circuit in systems. Cooling the circuits also increases in difficulty as circuits are packaged more densely. The good heat transfer charac- teristics of silicon in the chips, ceramic in the modules, and copper inner planes in the second-level package, along with a trend toward higherjunction temperatures, provided an evolutionary solution to this problem. However, in the latest generation (308 1 system) more dramatic innovations, including heat sinks and conduction cooling from the back of chips, have been required [9]. The packaging failure rates have been decreasing by orders of magnitude on a per-circuit basis. The reliability improvement has been made possible through use of IBM I. RES. DEVELOP. VOL. 25 NO. 5 SEPTEMBER 1981 Figure 4 The System/370 Model 148 MST electronic package. Up to 60 modules are mounted on printed circuit cards plugged into a printed circuit back panel. fewer components and a reduction in the total number of contacts between components. Because of this trend, field maintenance strategy has evolved to handle larger field-replaceable units (FRUs). Thus, quite large systems like the 4300 Series, announced by IBM in 1979 [6], provide all interconnection on one printed circuit back panel containing 16 planes. This entire back panel is a FRU, as are the printed circuit cards. In this paper we describe the progress in IBM in developing the chip carriers, show the progress in con- struction of printed-circuit back panels, and discuss the innovation in pluggable contact systems. From time to time we will reference the industry as a benchmark. This era covers computer systems from the IBM 1401 Series through IBM System/360, System/370,4300 Series, up to the 3081. The overall systems packaging concepts are shown in Figs. 2 through 6. First-level packaging Chip carriers for single devices The functions of the first-level package (or module) as a chip carrier are to provide the proper mechanical, ther- mal, and electrical environment while interconnecting the chip terminals and providing pins as a means of interfac- ing to the next level of package. The first chip carriers were small single-device carriers, hermetically sealed metal cans with chips wire-bonded to a ceramic base, glass-sealed, TO-5 or the like, and these were inserted and soldered directly into the next card level of package, as were the resistors, capacitors, and other discrete components. The next level of package Figure 5 The 4300 Series COB electronic package. Multilayer ceramic modules containing up to nine chips are soldered into printed circuit cards. The cards are plugged into printed circuit back panels. Figure 6 The 3081 System large planar board. Large Thermal Conduction Modules (TCMs) plug directly into the printed circuit back panel. integrated these into a pluggable functional circuit con- taining 6 to 15 transistors and as many resistors. This first- and second-level package [IO] in IBM in the late 1950s was called the Standard Modular System (SMS) and was made from paper epoxy containing etched cop- per circuitry on one side. Carriers for single circuits In 1964 IBM introduced Solid Logic Technology (SLT) [ll], which integrated the semiconductor and resistor 6i19 IBM J. RES. DEVELOP. VOL. 25 NO. 5 SEPTEMBER 1981 D. P. SERAPHIM AND I . FEINBERG card noted above. The module contained one circuit, as did the SMS card. The SLT module [ 111 was a pressed ceramic part with holes preformed for pins. This was a new and unique ceramic formulation with the required strength to with- stand pinning operations and the surface texture to meet the requirements of screen printing. It was screened with an interconnection pattern of gold platinum paste contain- ing a small amount of glass for adhesion. The paste formulations were designed for bond strength and electri- cal conductivity. The sintered paste interconnection was solderable, allowing metallic wetting to the pins and between the paste interconnection and the chip. The Figure 7 Progress of chip carriers developed by IBM in 1%0 to solder enhanced the conductivity of the interconnection 1980: chip devices per camer increased from one to nine, pins and provided sufficient ductility for fatigue life of the chip per camer increased from several to hundreds, circuits from less joint. Gold- and nickel-plated copper balls between the than one to thousands. Table 1 Chip packaging: SMS compared to SLT. SMS SLT Chip face up Chip face down Wire bond interconnection Solder bond interconnection Cooling through back bond Cooling through solder Discrete resistors Screened frit resistors Hermetic seal Glass seal on chip, cap crimped interconnection bonds to module, plastic seal components, providing the set of circuit functions de- sired, on a very small [12.5 X 12.5-mm (0.5 X OS-in.)] ceramic substrate which was exceptionally well suited for mass production. One of the main differences between SLT and its predecessor SMS was the introduction of a module to interconnect individual devices to form a circuit. These modules are called hybrid integrated cir- cuits. The individual devices in the modules were not separately housed in their own package as were SMS devices. Thus, a comparison (shown in Table 1) of SLT chip carriers (or modules) with SMS chip carriers high- lights what was new when IBM developed SLT and where IBM diverged from the approaches used by the rest of the electronics industry. This was the beginning of a unique technology base which broadened (Fig. 7) in subsequent generations as the demand for more chip connections increased. The SLT module in effect replaced the SMS printed circuit package 620 D. P. SERAPHIM AND I. FEINBERG chip and the module [12] created a positive stand-off to guarantee a soldered thickness for favorable fatigue behavior. A wide range of resistor pastes were formulated to meet pretrimming ohmic requirements. They were moni- tored through the pins while they were automatically trimmed by removal of material to a required resistance. The semiconductor chip devices were automatically oriented by the configuration of the terminals while they climbed a set of tracks in a vibrating bowl. They were picked up, tested, positioned, and soldered to the module interconnection patterns in one automatic machine. A solder melting point hierarchy for lands and pins was developed so that chips could be joined and modules later soldered into printed circuit cards without affecting the chip bonds. The module was finally encapsulated with a coating of silicon gel and placed in a crimped can with a silicone rubber filler poured into the periphery as a back seal. Corner pins were swaged to provide positive and con- trolled stand-off when soldered into printed circuit cards. This packaging hierarchy which built terminals and passivation into the device at the wafer level, combined with automatic chip joining to modules, resulted in a very high production capacity compared to that of convention- al wire bonding techniques. The glass-passivated chip devices not only made the ultimate product reliable but also made it possible to utilize an active solder flux, and, more importantly, allowed the use of a plastic (non- hermetic) seal for the module. The designs, process, and tools achieved very high yields. For example, module yields from chip joining to shipment were greater than 95%. IBM J. RES. DEVELOP. VOL. 25 NO. 5 SEPTEMBER 1981 Chip carriers f o r integrated circuit chips It was possible in 1969 to integrate up to 20 circuits on a Monolithic Systems Technology (MST) chip. According- ly, the chips grew in size and required up to 16 terminals for an average use of 6 or 7 circuits per chip. Copper balls used in SLT as terminals for the chips were then replaced with an evaporated solder joint, controlled collapse chip contact (C-4) [13, 141, which drew the chips into place by surface tension, allowing tighter interconnection toler- ances and also affording a fatigue-resistant interface to the module. The height of the C-4 solder pad (a critical parameter in the fatigue-resistant design) was controlled by the volume of solder and the pad area screened on the module [MI. This pad area was defined by the line width and a solder dam of screened and sintered glass frit crossing the interconnection line. The solder was partly supplied by wave-soldering the surface of the module, but the majority was supplied with the chips. For the first time, area array connections were made between the chip and the module to provide improved power supply to the center of the chips. The interconnection of the module was fanned out to an area array of pins. For memory use it was possible to interconnect four chips on a substrate and stack two substrates. This provided very aggressive densities and substantial sav- ings at the higher levels of packaging. The manufacturing techniques used for SLT were adaptable, with further developments, for MST and memory technology. By 1973 Metal Oxide Semiconductor Field Effect Tran- sistor (MOSFET) and bipolar device integration on semi- conductor chips had reached 100 to 200 circuits, requiring up to 76 interconnection pins on the modules. To mini- mize the module size, a 9 X 9 array of pins was supplied in a one-inch-square area. Center locations were left free of pins to make room for the chip site. The refined patterns and tolerances resulting from photolithographic technology (described below) allowed a double row of C- 4 pads to be used around the perimeter of the chip; power distribution could also be supplied on the module to the center of the chip. This was beyond that achievable with the tolerances from one layer of screened-frit thick-film technology. A new and extendible evaporated thin film (composite CrCuCr) on ceramic substrates was devised to supply all of the functions. The bottom layer of Cr acts as an adhesive to the ceramic while the top layer of Cr acts as a solder dam. The copper interlayer is superior in conduc- tivity compared to its paste predecessor and is also a better base for soldering. An automatic 5~ projection printer is used to define the interconnection pattern in the photoresist. A wide range of part numbers is easily adapted to the automatic exposure system. The general scheme initiated in SLT for chip orienting, locating, and joining was extended to meet mass production require- ments. A new epoxy back seal [16, 171, much less permeable than silicone rubber, was developed for the module. This seal design provides a compliant connection between the cap and the ceramic substrate, which have substantially different thermal expansion coefficients. While IBM pursued the metallized ceramic (MC) ap- proach, the dual in-line package (DIP) became the stan- dard of the industry through actions taken by the Joint Electron Device Engineering Council (JEDEC). The lead frame pins along the two edges of the DIP used to package vendor chips were compatible with the standard 100-mil grid used by IBM. The DIPs were used extensive- ly along with the MC. The DIPs were available either as plastic packages or as ceramic packages. However, while IBM was able to integrate freely to 76 and 96 pins in a less than 25 X 25-mm array, the DIPs were limited by their practical length dimensions of less than two inches, which allowed only 40 pins on the 100-mil grid on the two edges of the module. The demand for more interconnections brought on an alternative JEDEC industry standard pack- age utilizing all four edges of the chip carrier. These packages, with large arrays of pins, are becoming avail- able in the industry today [MI. Multichip-chip carriers for large-scale integration Integration has continued to increase, with density grow- ing to 500-700 bipolar circuits and several thousand MOSFET circuits per chip. Thus our Rent relationship (Fig. 1) projects the need for a continued growth in terminals to several hundred. To accommodate this growth the metallized ceramic technology has been ex- tended to 28-mm-square (Fig. 7) and later to 36-mm- square ceramic substrates with finer lines to handle the more closely spaced terminals on the chips. Finally, the use of chip terminals surpassed the capabil- ity to interconnect them on one interconnection layer on a module. At this juncture many new developments were required and a technology change had to be made that could be extended for future generations. Therefore, multilayer module technology introduced a multichip module which reduced the total packaging cost by de- creasing the use of higher levels of packaging, i . e . , cards, cables, and printed circuit boards. The added process steps of the multilayer technology increased the packaged cost per chip, but this cost was amortized over more than one chip, decreasing the cost per interconnection. IBM I. RES. DEVELOP. VOL. 25 NO. 5 SEPTEMBER 1981 Figur